Advanced Digital Design with the Verilog HDL (2nd Edition)

Description

For an advanced course in digital design for seniors and first-year graduate students in electrical engineering, computer engineering, and computer science.

This book builds on the student’s background from a first course in logic design and focuses on developing, verifying, and synthesizing designs of digital circuits. The Verilog language is introduced in an integrated, but ive manner, only as needed to support design examples (includes appendices for additional language details). It addresses the design of several important circuits used in computer systems, digital signal processing, image processing, and other applications.

Key Features

• Provides a brief review of basic principles in combinational and sequential logic
• Focuses on modern digital design methodology
• Demonstrates the utility of ASM and ASMD charts for behavioral modeling
• Clearly distinguishes between synthesizable and nonsynthesizable loops
• Provides several problems with a wide range of difficulty after each chapter
• Combines a solution manual with an on-line repository of additional worked exercises

Table of Contents

1. Introduction to Digital Design Methodology
2. Review of Combinational Logic Design
3. Fundamentals of Sequential Logic Design
4. Introduction to Logic Design with Verilog
5. Logic Design with Behavioral Models of Combinational and Sequential Logic
6. Synthesis of Combinational and Sequential Logic
7. Design and Synthesis of Datapath Controllers
8. Programmable Logic and Storage Devices
9. Algorithms and Architectures for Digital Processors
10. Architectures for Arithmetic Processors
11. Postsynthesis Design Tasks

Author Biography

Michael Ciletti is Professor Emeritus in the Department of Electrical and Computer Engineering at the University of Colorado, Colorado Springs. His areas of interest include Modeling, synthesis and verification of digital systems with hardware description languages, system-level design languages, and embedded systems with FPGAs.