Spacer Engineered FinFET Architectures

Description

This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.

Table of Contents

1. Preface
2. About the Authors
3. Chapter 1: Introduction to Nanoelectronics
4. Chapter 2: Tri-Gate FinFET Technology and Its Advancement
5. Chapter 3: Dual-k Spacer Device Architecture and Its Electrostatics
6. Chapter 4: Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design
7. Chapter 5: Design Metric Improvement of a Dual-k–Based SRAM Cell
8. Chapter 6: Statistical Variability and Sensitivity Analysis
9. Index